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| Freescale Semiconductor Advance Information MC9328MXS/D Rev. 0, 1/2005 MC9328MXS MC9328MXS Package Information Plastic Package (PBGA-225) Ordering Information See Table 2 on page 4 1 Introduction The i.MX (Media Extensions) series provides a leap in performance with an ARM9TM microprocessor core and highly integrated system functions. The i.MX products specifically address the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities. The i.MX processor features the advanced and powerefficient ARM920TTM core that operates at speeds up to 100 MHz. Integrated modules, which include a USB device and an LCD controller, support a suite of peripherals to enhance portable products. It is packaged in a 225-contact PBGA package. Figure 1 shows the functional block diagram of the i.MX processor. Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signals and Connections . . . . . . . . . . . . . . . . . . . .5 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pin-Out and Package Information . . . . . . . . . . . .69 Contact Information . . . . . . . . . . . . . . . . . Last Page (c) Freescale Semiconductor, Inc., 2005. All rights reserved. This document contains information on a new product. Specifications and information herein are subject to change without notice. Introduction Figure 1. MC9328MXS Functional Block Diagram 1.1 Conventions This document uses the following conventions: * * * * * * * * OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. -- Active low signals change from logic level one to logic level zero. -- Active high signals change from logic level zero to logic level one. * Negated means that an asserted discrete signal changes logic state. -- Active low signals change from logic level zero to logic level one. -- Active high signals change from logic level one to logic level zero. * * LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out. Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal. MC9328MXS Advance Information, Rev. 0 2 Freescale Semiconductor Introduction 1.2 Features To support a wide variety of applications, the i.MX processor offers a robust array of features, including the following: * * * * * * * * * * * * * * * * * * * * * ARM920TTM Microprocessor Core AHB to IP Bus Interfaces (AIPIs) External Interface Module (EIM) SDRAM Controller (SDRAMC) DPLL Clock and Power Control Module Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2) Serial Peripheral Interface (SPI) Two General-Purpose 32-bit Counters/Timers Watchdog Timer Real-Time Clock/Sampling Timer (RTC) LCD Controller (LCDC) Pulse-Width Modulation (PWM) Module Universal Serial Bus (USB) Device Direct Memory Access Controller (DMAC) Synchronous Serial Interface and Inter-IC Sound (SSI/I2S) Module Inter-IC (I2C) Bus Module General-Purpose I/O (GPIO) Ports Bootstrap Mode Power Management Features Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O 225-contact PBGA Package 1.3 Target Applications The i.MX processor is targeted for advanced information appliances, smart phones, Web browsers, and messaging applications. 1.4 Revision History Table 1 provides revision history for this release. This history includes technical content revisions only and not stylistic or grammatical changes. Table 1. MC9328MXS Data Sheet Revision History for Rev. 0 Revision Initial Release MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 3 Introduction 1.5 Reference Documents The following documents are required for a complete description of the MC9328MXS and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall products, the following documents are helpful when used in conjunction with this document. ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100) ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029) ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C) EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E) MC9328MXS Product Brief (order number MC9328MXSP/D) MC9328MXS Reference Manual (order number MC9328MXSRM/D) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com. 1.6 Ordering Information Table 2 provides ordering information for the 225-contact PBGA package. Table 2. MC9328MXS Ordering Information Package Type 225-contact PBGA Frequency 100 MHz Temperature -40OC to 85OC Solderball Type Standard Pb-free 0OC to 70OC Standard Pb-free 1. Contact your distribution center or Freescale sales office. Order Number MC9328MXSCVF10(R2) See Note1 MC9328MXSVF10(R2) See Note1 MC9328MXS Advance Information, Rev. 0 4 Freescale Semiconductor Signals and Connections 2 Signals and Connections Table 3 identifies and describes the i.MX processor signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to. Table 3. MC9328MXS Signal Descriptions Signal Name Function/Notes External Bus/Chip-Select (EIM) A[24:0] D[31:0] EB0 EB1 EB2 EB3 OE CS [5:0] ECB LBA BCLK (burst clock) RW DTACK Address bus signals Data bus signals MSB Byte Strobe--Active low external enable byte signal that controls D [31:24]. Byte Strobe--Active low external enable byte signal that controls D [23:16]. Byte Strobe--Active low external enable byte signal that controls D [15:8]. LSB Byte Strobe--Active low external enable byte signal that controls D [7:0]. Memory Output Enable--Active low output enables external data bus. Chip-Select--The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected. Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. Active low signal sent by a flash device causing the external burst device to latch the starting burst address. Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW signal--Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM. DTACK signal--The external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clock counts have elapsed. Bootstrap BOOT [3:0] System Boot Mode Select--The operational system boot mode of the i.MX processor upon system reset is determined by the settings of these pins. SDRAM Controller SDBA [4:0] SDIBA [3:0] MA [11:10] MA [9:0] DQM [3:0] CSD0 CSD1 SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM cycles. SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles. SDRAM address signals SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on SDRAM cycles. SDRAM data enable SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register. SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected, so it can be used as boot chip-select by properly configuring BOOT [3:0] input pins. SDRAM Row Address Select signal RAS MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 5 Signals and Connections Table 3. MC9328MXS Signal Descriptions (Continued) Signal Name CAS SDWE SDCKE0 SDCKE1 SDCLK RESET_SF SDRAM Column Address Select signal SDRAM Write Enable signal SDRAM Clock Enable 0 SDRAM Clock Enable 1 SDRAM Clock Not Used Clocks and Resets EXTAL16M XTAL16M EXTAL32K XTAL32K CLKO RESET_IN RESET_OUT POR Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut down. Crystal output 32 kHz crystal input 32 kHz crystal output Clock Out signal selected from internal clock signals. Master Reset--External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module and the clock control module) are reset. Reset Out--Internal active low output signal from the Watchdog Timer module and is asserted from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. Power On Reset--Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event. JTAG TRST TDO TDI TCK TMS Test Reset Pin--External active low signal used to asynchronously initialize the JTAG controller. Serial Output for test instructions and data. Changes on the falling edge of TCK. Serial Input for test instructions and data. Sampled on the rising edge of TCK. Test Clock to synchronize test logic and control register access through the JTAG port. Test Mode Select to sequence the JTAG test controller's state machine. Sampled on the rising edge of TCK. DMA BIG_ENDIAN Big Endian--Input signal that determines the configuration of the external chip-select space. If it is driven logic-high at reset, the external chip-select space will be configured to little endian. If it is driven logic-low at reset, the external chip-select space will be configured to big endian. External DMA request pin. ETM ETMTRACESYNC ETMTRACECLK ETMPIPESTAT [2:0] ETMTRACEPKT [7:0] ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode. ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode. ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM mode. ETM packet signals which are multiplexed with ECB, LBA, BCLK(burst clock), PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. LCD Controller LD [15:0] LCD Data Bus--All LCD signals are driven low after reset and when LCD is off. Function/Notes DMA_REQ MC9328MXS Advance Information, Rev. 0 6 Freescale Semiconductor Signals and Connections Table 3. MC9328MXS Signal Descriptions (Continued) Signal Name FLM/VSYNC LP/HSYNC LSCLK ACD/OE CONTRAST SPL_SPR PS CLS REV SPI1_MOSI SPI1_MISO SPI1_SS SPI1_SCLK SPI1_SPI_RDY Function/Notes Frame Sync or Vsync--This signal also serves as the clock signal output for the gate driver (dedicated signal SPS for Sharp panel HR-TFT). Line pulse or H sync Shift clock Alternate crystal direction/output enable. This signal is used to control the LCD bias voltage as contrast control. Program horizontal scan direction (Sharp panel dedicated signal). Control signal output for source driver (Sharp panel dedicated signal). Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated signal). Signal for common electrode driving signal preparation (Sharp panel dedicated signal). SPI 1 Master Out/Slave In Slave In/Master Out Slave Select (Selectable polarity) Serial Clock Serial Data Ready General Purpose Timers TIN TMR2OUT USBD_VMO USBD_VPO USBD_VM USBD_VP USBD_SUSPND USBD_RCV USBD_OE USBD_AFE UART1_RXD UART1_TXD UART1_RTS UART1_CTS UART2_RXD UART2_TXD UART2_RTS UART2_CTS UART2_DSR Timer Input Capture or Timer Input Clock--The signal on this input is applied to both timers simultaneously. Timer 2 Output USB Device USB Minus Output USB Plus Output USB Minus Input USB Plus Input USB Suspend Output USB Receive Data USB OE USB Analog Front End Enable UARTs - IrDA/Auto-Bauding Receive Data Transmit Data Request to Send Clear to Send Receive Data Transmit Data Request to Send Clear to Send Data Set Ready MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 7 Signals and Connections Table 3. MC9328MXS Signal Descriptions (Continued) Signal Name UART2_RI UART2_DCD UART2_DTR SSI_TXDAT SSI_RXDAT SSI_TXCLK SSI_RXCLK SSI_TXFS SSI_RXFS Ring Indicator Data Carrier Detect Data Terminal Ready Serial Audio Port - SSI (configurable to I2S protocol) Transmit Data Receive Data Transmit Serial Clock Receive Serial Clock Transmit Frame Sync Receive Frame Sync I2C I2C_SCL I2C_SDA I2C Clock I2C Data PWM PWMO PWM Output Test Function TRISTATE Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input with a 1 k ohm resistor to ground. (TRI-STATE(R) is a registered trademark of National Semiconductor.) General Purpose Input/Output PA[14:3] PB[13:8] Dedicated GPIO Dedicated GPIO Digital Supply Pins NVDD NVSS Digital Supply for the I/O pins Digital Ground for the I/O pins Supply Pins - Analog Modules AVDD AVSS Supply for analog blocks Quiet ground for analog blocks Internal Power Supply QVDD QVSS Power supply pins for silicon internal circuitry Ground pins for silicon internal circuitry Substrate Supply Pins SVDD SGND Supply routed through substrate of package; not to be bonded Ground routed through substrate of package; not to be bonded Function/Notes MC9328MXS Advance Information, Rev. 0 8 Freescale Semiconductor Specifications 3 Specifications This section contains the electrical specifications and timing diagrams for the i.MX processor. 3.1 Maximum Ratings Table 4 provides information on maximum ratings which are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5 on page 9 or the DC Characteristics table. Table 4. Maximum Ratings Symbol NVDD QVDD AVDD BTRFVDD VESD_HBM VESD_MM ILatchup Test Pmax 1. 2. DC I/O Supply Voltage DC Internal (core = 100 MHz) Supply Voltage DC Analog Supply Voltage DC Bluetooth Supply Voltage ESD immunity with HBM (human body model) ESD immunity with MM (machine model) Latch-up immunity Storage temperature Power Consumption Rating Minimum -0.3 -0.3 -0.3 -0.3 - - - -55 8001 Maximum 3.3 1.9 3.3 3.3 2000 100 200 150 13002 Unit V V V V V V mA C mW A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM(R) core-that is, 7x GPIO, 15x Data bus, and 8x Address bus. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS application at 100MHz, and where the whole image is running out of SDRAM. QVDD at 1.9V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA. 3.2 Recommended Operating Range Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MX processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system. Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the AVDD pins from other VDD pins. For more information about I/O pads grouping per VDD, please refer to Table 3 on page 5. Table 5. Recommended Operating Range Symbol TA Operating temperature range MC9328MXSVF10 Rating Minimum 0 Maximum 70 Unit C MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 9 Specifications Table 5. Recommended Operating Range (Continued) Symbol TA NVDD NVDD QVDD AVDD Operating temperature range MC9328MXSCVF10 I/O supply voltage (if using SPI, LCD, and USBd which are only 3 V interfaces) I/O supply voltage (if not using the peripherals listed above) Internal supply voltage (Core = 100 MHz) Analog supply voltage Rating Minimum -40 2.70 1.70 1.70 1.70 Maximum 85 3.30 3.30 1.90 3.30 Unit C V V V V 3.3 Power Sequence Requirements For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of application note AN2537 on the i.MX application processor website. 3.4 DC Electrical Characteristics Table 6 contains both maximum and minimum DC characteristics of the i.MX processor. Table 6. Maximum and Minimum DC Characteristics Number or Symbol Iop Parameter Full running operating current at 1.8V for QVDD, 3.3V for NVDD/AVDD (Core = 96 MHz, System = 96 MHz, driving TFT display panel, and OS with MMU enabled memory system is running on external SDRAM). Standby current (Core = 100 MHz, QVDD = 1.8V, temp = 25C) Standby current (Core = 100 MHz, QVDD = 1.8V, temp = 55C) Standby current (Core = 100 MHz, QVDD = 1.9V, temp = 25C) Standby current (Core = 100 MHz, QVDD = 1.9V, temp = 55C) Input high voltage Input low voltage Output high voltage (IOH = 2.0 mA) Output low voltage (IOL = -2.5 mA) Input low leakage current (VIN = GND, no pull-up or pull-down) Min - Typical QVDD at 1.8V = 120mA; NVDD+AVDD at 3.0V = 30mA 25 Max - Unit mA Sidd1 Sidd2 Sidd3 Sidd4 VIH VIL VOH VOL IIL - - A A A A - 45 - - 35 - - 60 - 0.7VDD - 0.7VDD - - - - - - - Vdd+0.2 0.4 Vdd 0.4 1 V V V V A MC9328MXS Advance Information, Rev. 0 10 Freescale Semiconductor Specifications Table 6. Maximum and Minimum DC Characteristics (Continued) Number or Symbol IIH IOH IOL IOZ Ci Co Parameter Input high leakage current (VIN = VDD, no pull-up or pull-down) Output high current (VOH = 0.8VDD, VDD = 1.8V) Output low current (VOL = 0.4V, VDD = 1.8V) Output leakage current (Vout = VDD, output is high impedence) Input capacitance Output capacitance Min - Typical - Max 1 Unit A - - 4.0 mA -4.0 - - mA A - - 5 - - - - 5 5 pF pF 3.5 AC Electrical Characteristics The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of other signals. All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 100 MHz) with an operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading. Table 7. Tristate Signal Timing Pin TRISTATE Parameter Time from TRISTATE activate until I/O becomes Hi-Z Minimum - Maximum 20.8 Unit ns Table 8. 32k/16M Oscillator Signal Timing Parameter EXTAL32k input jitter (peak to peak) EXTAL32k startup time EXTAL16M input jitter (peak to peak) 1 EXTAL16M startup time 1 1. Minimum - 800 - TBD RMS 5 - TBD - Maximum 20 - TBD - Unit ns ms - - The 16 MHz oscillator is not recommended for use in new designs. MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 11 Specifications 3.6 Embedded Trace Macrocell All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the ARM920T processor's TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift register comprised of the following: * * * 32-bit data field 7-bit address field A read/write bit The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used in Figure 2. 2a 3a TRACECLK 1 2b 3b TRACECLK (Half-Rate Clocking Mode) Output Trace Port Valid Data Valid Data 4a 4b Figure 2. Trace Port Timing Diagram Table 9. Trace Port Timing Diagram Parameter Table Ref No. 1 2a 2b 3a 3b 4a 4b 1.8 0.1 V Parameter Minimum CLK frequency Clock high time Clock low time Clock rise time Clock fall time Output hold time Output setup time 0 1.3 3 - - 2.28 3.42 Maximum 85 - - 4 3 - - Minimum 0 2 2 - - 2 3 Maximum 100 - - 3 3 - - MHz ns ns ns ns ns ns 3.0 0.3 V Unit MC9328MXS Advance Information, Rev. 0 12 Freescale Semiconductor Specifications 3.7 DPLL Timing Specifications Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the pre-divider and Tdck is the output double clock period. Table 10. DPLL Specifications Parameter Reference clock freq range Pre-divider output clock freq range Double clock freq range Pre-divider factor (PD) Total multiplication factor (MF) MF integer part MF numerator MF denominator Pre-multiplier lock-in time Freq lock-in time after full reset Freq lock-in time after partial reset Phase lock-in time after full reset Phase lock-in time after partial reset Freq jitter (p-p) Vcc = 1.8V Vcc = 1.8V Test Conditions Minimum 5 5 Typical - - Maximum 100 30 Unit MHz MHz Vcc = 1.8V - Includes both integer and fractional parts - Should be less than the denominator - - FOL mode for non-integer MF (does not include pre-multi lock-in time) FOL mode for non-integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) - 80 1 5 5 0 1 - 250 - - - - - - - 280 (56 s) 250 (50 s) 350 (70 s) 320 (64 s) 0.005 (0.01%) 1.0 (10%) - - 220 16 15 15 1022 1023 312.5 300 MHz - - - - - sec Tref Tref Tref Tref 2*Tdck ns 220 270 300 400 270 370 - 0.01 Phase jitter (p-p) Integer MF, FPL mode, Vcc=1.8V - 1.5 Power supply voltage Power dissipation - FOL mode, integer MF, fdck = 100 MHz, Vcc = 1.8V 1.7 - 2.5 4 V mW MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 13 Specifications 3.8 Reset Module The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4. NOTE: Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent forward biasing. 90% AVDD 1 POR 10% AVDD RESET_POR 2 Exact 300ms RESET_DRAM 3 7 cycles @ CLK32 HRESET RESET_OUT 4 14 cycles @ CLK32 CLK32 HCLK Figure 3. Timing Relationship with POR MC9328MXS Advance Information, Rev. 0 14 Freescale Semiconductor Specifications 5 RESET_IN 14 cycles @ CLK32 HRESET RESET_OUT 4 6 CLK32 HCLK Figure 4. Timing Relationship with RESET_IN Table 11. Reset Module Timing Parameter Table Ref No. 1 2 3 4 5 6 1. 1.8 0.1 V Parameter Min Width of input POWER_ON_RESET Width of internal POWER_ON_RESET (CLK32 at 32 kHz) 7K to 32K-cycle stretcher for SDRAM reset 14K to 32K-cycle stretcher for internal system reset HRESERT and output reset at pin RESET_OUT Width of external hard-reset RESET_IN 4K to 32K-cycle qualifier note1 300 7 14 4 4 Max - 300 7 14 - 4 Min note1 300 7 14 4 4 Max - 300 7 14 - 4 - ms Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 3.0 0.3 V Unit POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals. Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal. If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in calculating timing for the start-up process. MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 15 Specifications 3.9 External Interface Module The External Interface Module (EIM) handles the interface to devices external to the i.MX processor, including the generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 12 on page 16 defines the parameters of signals. (HCLK) Bus Clock 1a 1b Address Chip-select 2a 2b 3a 3b Read (Write) OE (rising edge) OE (falling edge) EB (rising edge) EB (falling edge) 6a 5a 4a 4b 4c 4d 5b 5c 5d LBA (negated falling edge) 6b LBA (negated rising edge) 6a 6c 7a 7b BCLK (burst clock) - rising edge BCLK (burst clock) - falling edge 7c 7d 8b Read Data 9a 8a 9b Write Data (negated falling) 9a 9c Write Data (negated rising) DTACK_B 10a 10a Figure 5. EIM Bus Timing Diagram Table 12. EIM Bus Timing Parameter Table 1.8 0.1 V Ref No. 1a 1b Parameter Min Clock fall to address valid Clock fall to address invalid 2.48 1.55 Typical 3.31 2.48 Max 9.11 5.69 Min 2.4 1.5 Typical 3.2 2.4 Max 8.8 5.5 ns ns 3.0 0.3 V Unit MC9328MXS Advance Information, Rev. 0 16 Freescale Semiconductor Specifications Table 12. EIM Bus Timing Parameter Table (Continued) 1.8 0.1 V Ref No. 2a 2b 3a 3b 4a 4b 4c 4d 5a 5b 5c 5d 6a 6b 6c 7a 7b 7c 7d 8a 8b 9a 9b 9c 10a 1. Parameter Min Clock fall to chip-select valid Clock fall to chip-select invalid Clock fall to Read (Write) Valid Clock fall to Read (Write) Invalid Clock rise to Output Enable Valid Clock1 rise to Output Enable Invalid Clock fall to Output Enable Valid Clock fall to Output Enable Invalid Clock1 rise to Enable Bytes Valid Clock1 rise to Enable Bytes Invalid Clock fall to Enable Bytes Valid Clock1 fall to Enable Bytes Invalid 1 1 1 1 3.0 0.3 V Unit Max 7.87 6.31 6.52 6.11 6.85 6.55 7.04 6.73 5.54 5.24 5.69 5.38 6.73 6.83 6.45 5.64 5.84 5.59 5.80 - - 6.85 5.69 - - Min 2.6 1.5 1.3 1.8 2.3 2.1 2.3 2.1 1.9 1.8 1.9 1.7 2.0 1.9 1.9 1.6 1.6 1.5 1.5 5.5 0 1.8 1.4 1.62 2.5 Typical 3.2 2.4 2.7 2.5 2.6 2.5 2.6 2.5 2.5 2.4 2.5 2.4 2.7 2.7 2.6 2.6 2.6 2.4 2.5 - - 2.7 2.4 - - Max 7.6 6.1 6.3 5.9 6.8 6.5 6.8 6.5 5.5 5.2 5.5 5.2 6.5 6.6 6.4 5.6 5.8 5.4 5.6 - - 6.8 5.5 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Typical 3.31 2.48 2.79 2.59 2.62 2.52 2.69 2.59 2.52 2.42 2.59 2.48 2.79 2.79 2.62 2.62 2.62 2.48 2.59 - - 2.72 2.48 - - 2.69 1.55 1.35 1.86 2.32 2.11 2.38 2.17 1.91 1.81 1.97 1.76 2.07 1.97 1.91 1.61 1.61 1.55 1.55 5.54 0 1.81 1.45 1.63 2.52 Clock1 fall to Load Burst Address Valid Clock1 fall to Load Burst Address Invalid Clock1 1 rise to Load Burst Address Invalid Clock rise to Burst Clock rise Clock 1rise to Burst Clock fall Clock1 fall to Burst Clock rise Clock fall to Burst Clock fall Read Data setup time Read Data hold time Clock1 rise to Write Data Valid Clock fall to Write Data Invalid Clock1 rise to Write Data Invalid 1 1 DTACK setup time Clock refers to the system clock signal, HCLK, generated from the System DPLL MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 17 Specifications 3.9.1 DTACK Signal Description The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal function when the external DTACK signal is used for data acknowledgement. 3.9.2 DTACK Signal Timing Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of measure for this figure are found in the associated tables. MC9328MXS Advance Information, Rev. 0 18 Freescale Semiconductor Specifications 3.9.2.1 DTACK Read Cycle without DMA 3 Address 2 CS5 8 1 EB programmable min 0ns 5 4 9 OE DTACK DATABUS (input to i.MX) 10 6 7 Figure 6. DTACK Read Cycle without DMA Table 13. Read Cycle without DMA: WSC = 111111, DTACK_SEL=0, HCLK=96MHz 3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 Characteristic Minimum OE and EB assertion time CS5 pulse width OE negated to address inactive DTACK asserted after CS5 asserted DTACK asserted to OE negated Data hold timing after OE negated Data ready after DTACK asserted OE negated to CS negated OE negated after EB negated DTACK pulse width See note 3 3T 46.39 - 3T+1.83 0 0 0.5T-0.68 0.06 1T Maximum - - - 1019T 4T+6.6 - T 0.5T-0.06 0.18 3T ns ns ns ns ns ns ns ns ns ns Unit Note: 1. DTACK asserted means DTACK becomes low level. 2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 3. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 4. Address becomes valid and CS asserts at the start of read access cycle. 5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 19 Specifications 3.9.2.2 DTACK Read Cycle DMA Enabled 4 Address 2 CS5 9 10 3 6 1 EB programmable min 0ns OE RW (logic high) DTACK 5 7 11 DATABUS (input to i.MX) 8 Figure 7. DTACK Read Cycle DMA Enabled Table 14. Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=0, HCLK=96MHz 3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 Characteristic Minimum OE and EB assertion time CS pulse width OE negated before CS5 is negated Address inactive before CS negated DTACK asserted after CS5 asserted DTACK asserted to OE negated Data hold timing after OE negated Data ready after DTACK is asserted CS deactive to next CS active OE negate after EB negate DTACK pulse width See note 3 3T 0.5T-0.68 - - 3T+1.83 0 - T 0.06 1T Maximum - - 0.5T-0.06 0.3 1019T 4T+6.6 - T - 0.18 3T ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. DTACK asserted means DTACK becomes low level. 2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 3. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 4. Address becomes valid and CS asserts at the start of read access cycle. 5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXS Advance Information, Rev. 0 20 Freescale Semiconductor Specifications 3.9.2.3 DTACK Write Cycle without DMA 5 Address 1 CS5 3 programmable min 0ns 10 2 EB programmable min 0ns 4 7 RW OE (logic high) DTACK 6 11 8 Databus (input to i.MX) 9 Figure 8. DTACK Write Cycle without DMA Table 15. Write Cycle without DMA: WSC = 111111, DTACK_SEL=0, HCLK=96MHz 3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 Characteristic Minimum CS5 assertion time EB assertion time CS5 pulse width RW negated before CS5 is negated RW negated to address inactive DTACK asserted after CS5 asserted DTACK asserted to RW negated Data hold timing after RW negated Data ready after CS5 is asserted EB negated after CS5 is negated DTACK pulse width See note 3 See note 3 3T 1.5T-2.44 57.31 - 2T+2.37 1.5T-3.99 - 0.5T 1T Maximum - - - 1.5T-0.8 - 1019T 3T+6.6 - T 0.5T+0.5 3T ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. DTACK asserted means DTACK becomes low level. 2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 3. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register. 4. Address becomes valid and RW asserts at the start of write access cycle. 5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 21 Specifications 3.9.2.4 DTACK Write Cycle DMA Enabled 5 Address 1 CS5 programmable min 0ns programmable min 0ns 3 10 2 EB 11 4 RW 7 OE (logic high) DTACK 6 9 12 8 DATABUS (output to i.MX) Figure 9. DTACK Write Cycle DMA Enabled Table 16. Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=0, HCLK=96MHz 3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 12 Characteristic Minimum CS5 assertion time EB assertion time CS5 pulse width RW negated before CS5 is negated Address inactive after CS negated DTACK asserted after CS5 asserted DTACK asserted to RW negated Data hold timing after RW negated Data ready after CS5 is asserted CS deactive to next CS active EB negate after CS negate DTACK pulse width See note 3 See note 3 3T 1.5T-2.44 - - 2T+2.37 1.5T-3.99 - T 0.5T 1T Maximum - - - 1.5T-0.8 0.3 1019T 3T+6.6 - T - 0.5T+0.5 3T ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. DTACK asserted means DTACK becomes low level. 2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 3. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register. 4. Address becomes valid and RW asserts at the start of write access cycle. 5.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXS Advance Information, Rev. 0 22 Freescale Semiconductor Specifications 3.9.2.5 WAIT Read Cycle without DMA 3 Address 2 CS5 8 1 EB programmable min 0ns 9 5 OE 4 WAIT 7 DATABUS (input to i.MX) 6 10 11 Figure 10. WAIT Read Cycle without DMA Table 17. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz 3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 Characteristic Minimum OE and EB assertion time CS5 pulse width OE negated to address inactive Wait asserted after OE asserted Wait asserted to OE negated Data hold timing after OE negated Data ready after wait asserted OE negated to CS negated OE negated after EB negated Become low after CS5 asserted Wait pulse width See note 2 3T 56.81 - 2T+1.57 T-1.49 0 1.5T-0.68 0.06 0 1T Maximum - - 57.28 1020T 3T+7.33 - T 1.5T-0.06 0.18 1019T 1020T ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 3. Address becomes valid and CS asserts at the start of read access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 23 Specifications 3.9.2.6 WAIT Read Cycle DMA Enabled 4 Address 2 CS5 9 10 3 6 1 EB programmable min 0ns OE RW (logic high) WAIT 5 11 7 8 12 (input to i.MX) DATABUS Figure 11. WAIT Read Cycle DMA Enabled Table 18. WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz 3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 12 Characteristic Minimum OE and EB assertion time CS pulse width OE negated before CS5 is negated Address inactived before CS negated Wait asserted after CS5 asserted Wait asserted to OE negated Data hold timing after OE negated Data ready after wait is asserted CS deactive to next CS active OE negate after EB negate Wait becomes low after CS5 asserted Wait pulse width See note 2 3T 1.5T-0.68 - - 2T+1.57 T-1.49 - T 0.06 0 1T 0.18 1019T 1020T Maximum - - 1.5T-0.06 0.05 1020T 3T+7.33 - T ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 3. Address becomes valid and CS asserts at the start of read access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXS Advance Information, Rev. 0 24 Freescale Semiconductor Specifications 3.9.2.7 WAIT Write Cycle without DMA 5 Address 1 CS5 programmable min 0ns 2 3 EB programmable min 0ns 7 4 10 RW OE (logic high) WAIT 6 11 9 12 8 DATABUS (output to i.MX) Figure 12. WAIT Write Cycle without DMA Table 19. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz 3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 12 Characteristic Minimum CS5 assertion time EB assertion time CS5 pulse width RW negated before CS5 is negated RW negated to Address inactive Wait asserted after CS5 asserted Wait asserted to RW negated Data hold timing after RW negated Data ready after CS5 is asserted EB negated after CS5 is negated Wait becomes low after CS5 asserted Wait pulse width See note 2 See note 2 3T 2.5T-3.63 64.22 - T+2.66 2T+0.03 - 0.5T 0 1T Maximum - - - 2.5T-1.16 - 1020T 2T+7.96 - T 0.5T+0.5 1019T 1020T ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programable by WEA bits in CS5L register. 3. Address becomes valid and RW asserts at the start of write access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 25 Specifications 3.9.2.8 WAIT Write Cycle DMA Enabled 5 Address 1 CS5 programmable min 0ns programmable min 0ns 3 10 2 EB 11 7 RW 4 OE (logic high) WAIT 6 12 9 DATABUS (output to i.MX) 13 8 Figure 13. WAIT Write Cycle DMA Enabled Table 20. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz 3.0 0.3 V Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Characteristic Minimum CS5 assertion time EB assertion time CS5 pulse width RW negated before CS5 is negated Address inactived after CS negated Wait asserted after CS5 asserted Wait asserted to RW negated Data hold timing after RW negated Data ready after CS5 is asserted CS deactive to next CS active EB negate after CS negate Wait becomes low after CS5 asserted Wait pulse width See note 2 See note 2 3T 2.5T-3.63 - - T+2.66 2T+0.03 - T 0.5T 0 1T Maximum - - - 2.5T-1.16 0.09 1020T 2T+7.96 - T - 0.5T+0.5 1019T 1020T ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns) 2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programable by WEA bits in CS5L register. 3. Address becomes valid and RW asserts at the start of write access cycle. 4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. MC9328MXS Advance Information, Rev. 0 26 Freescale Semiconductor Specifications 3.9.3 EIM External Bus Timing The following timing diagrams show the timing of accesses to memory or a peripheral. hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[0] htrans Seq/Nonseq hwrite Read haddr hready weim_hrdata weim_hready V1 Last Valid Data V1 BCLK (burst clock) ADDR CS2 R/W Last Valid Address V1 Read LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA V1 Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 14. WSC = 1, A.HALF/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 27 Specifications hclk hsel_weim_cs[0] Internal signals - shown only for illustrative purposes htrans hwrite haddr Nonseq Write V1 hready hwdata weim_hrdata Last Valid Data Write Data (V1) Unknown Last Valid Data weim_hready BCLK (burst clock) ADDR CS0 R/W LBA Write Last Valid Address V1 OE EB DATA Last Valid Data Write Data (V1) Figure 15. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF MC9328MXS Advance Information, Rev. 0 28 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[0] htrans hwrite haddr Nonseq Read V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK (burst clock) ADDR CS0 Last Valid Addr Address V1 Address V1 + 2 R/W LBA OE Read EBx1 (EBC2=0) EBx1 (EBC2=1) DATA 1/2 Half Word 2/2 Half Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 16. WSC = 1, OEA = 1, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 29 Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[0] Nonseq htrans hwrite haddr Write V1 hready hwdata weim_hrdata Last Valid Data Write Data (V1 Word) Last Valid Data weim_hready BCLK (burst clock) ADDR CS0 Last Valid Addr Address V1 Address V1 + 2 R/W LBA OE Write EB DATA 1/2 Half Word 2/2 Half Word Figure 17. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 30 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[3] htrans hwrite haddr Nonseq Read V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK (burst clock) ADDR Last Valid Addr CS[3] R/W Read Address V1 Address V1 + 2 BA OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA 1/2 Half Word 2/2 Half Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 18. WSC = 3, OEA = 2, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 31 Specifications hclk hsel_weim_cs[3] htrans hwrite haddr hready hwdata Last Valid Data weim_hrdata Nonseq Internal signals - shown only for illustrative purposes Write V1 Write Data (V1 Word) Last Valid Data weim_hready BCLK (burst clock) ADDR Last Valid Addr CS3 R/W LBA OE Write Address V1 Address V1 + 2 EB DATA Last Valid Data 1/2 Half Word 2/2 Half Word Figure 19. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 32 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq Read hwrite haddr V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK (burst clock) ADDR CS2 R/W Read Last Valid Addr Address V1 Address V1 + 2 LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) weim_data_in 1/2 Half Word 2/2 Half Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 20. WSC = 3, OEA = 4, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 33 Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq hwrite haddr Write V1 hready hwdata Last Valid Data weim_hrdata Write Data (V1 Word) Last Valid Data weim_hready BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2 R/W LBA OE Write EB DATA Last Valid Data 1/2 Half Word 2/2 Half Word Figure 21. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 34 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq Read V1 hwrite haddr hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V1 + 2 CS2 Read R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA 1/2 Half Word 2/2 Half Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 22. WSC = 3, OEN = 2, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 35 Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq Read hwrite haddr V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK (burst clock) ADDR CS2 Read Last Valid Addr Address V1 Address V1 + 2 R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA 1/2 Half Word 2/2 Half Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 23. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 36 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq Write hwrite haddr V1 hready Last Valid Data hwdata weim_hrdata Write Data (V1 Word) Unknown Last Valid Data weim_hready BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2 R/W Write LBA OE EB DATA Last Valid Data 1/2 Half Word 2/2 Half Word Figure 24. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 37 Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Nonseq Write hwrite haddr V1 hready hwdata Last Valid Data weim_hrdata Write Data (V1 Word) Last Valid Data Unknown weim_hready BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2 R/W Write LBA OE EB DATA Last Valid Data 1/2 Half Word 2/2 Half Word Figure 25. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 38 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] Nonseq Read Nonseq Write htrans hwrite haddr V1 V8 hready hwdata weim_hrdata Last Valid Data Last Valid Data Write Data Read Data weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V8 CS2 R/W LBA Read Write OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA Read Data DATA Last Valid Data Write Data Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 26. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 39 Specifications Read hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] Idle Write htrans Nonseq Read Nonseq Write hwrite haddr V1 V8 hready hwdata Last Valid Data Write Data weim_hrdata Last Valid Data Read Data weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V8 CS2 R/W LBA Read Write OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA DATA Read Data Last Valid Data Write Data Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 27. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF MC9328MXS Advance Information, Rev. 0 40 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4] htrans Nonseq Write hwrite haddr V1 hready hwdata Last Valid Data weim_hrdata Write Data (Word) Last Valid Data weim_hready BCLK (burst clock) ADDR CS Last Valid Addr Address V1 Address V1 + 2 R/W Write LBA OE EB DATA Last Valid Data Write Data (1/2 Half Word) Write Data (2/2 Half Word) Figure 28. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 41 Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4] htrans Nonseq Read Nonseq Write hwrite haddr V1 V8 hready hwdata weim_hrdata weim_hready Last Valid Data Last Valid Data Write Data Read Data BCLK (burst clock) ADDR CS4 Last Valid Addr Address V1 Address V8 R/W LBA Read Write OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA Read Data DATA Last Valid Data Write Data Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 29. WSC = 3, CSA = 1, A.HALF/E.HALF MC9328MXS Advance Information, Rev. 0 42 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4] htrans Nonseq Read Idle Seq Read hwrite haddr V1 V2 hready weim_hrdata weim_hready Last Valid Data Read Data (V1) Read Data (V2) BCLK (burst clock) ADDR Last Valid Address V1 CNC Address V2 CS4 Read R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) DATA Read Data (V1) Read Data (V2) Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 30. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 43 Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4] htrans Nonseq Read Idle Nonseq Write hwrite haddr V1 V8 hready hwdata weim_hrdata Last Valid Data Last Valid Data Write Data Read Data weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 CNC CS4 R/W LBA OE Address V8 Read Write EBx1 (EBC2=0) EBx1 (EBC2=1) DATA DATA Read Data Last Valid Data Write Data Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 31. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF MC9328MXS Advance Information, Rev. 0 44 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans hwrite haddr Nonseq Read V1 Nonse Read V5 Idle hready weim_hrdata weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V5 CS2 Read R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) ECB DATA V1 Word V2 Word V5 Word V6 Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 32. WSC = 3, SYNC = 1, A.HALF/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 45 Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans hwrite haddr Idle Nonseq Read V1 Seq Read V2 Seq Read V3 Seq Read V4 hready weim_hrdata weim_hready BCLK (burst clock) Last Valid Data V1 Word V2 Word V3 Word V4 Word ADDR Last Valid Addr CS2 R/W Address V1 Read LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) ECB DATA V1 Word V2 Word V3 Word V4 Word Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 33. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD MC9328MXS Advance Information, Rev. 0 46 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Idle Nonseq Seq hwrite haddr Read V1 Read V2 hready weim_hrdata Last Valid Data V1 Word V2 Word weim_hready BCLK (burst clock) ADDR CS2 Read Last Valid Address V1 Address V2 R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) ECB DATA V1 1/2 V1 2/2 V2 1/2 V2 2/2 Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 34. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 47 Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] Non seq Read htrans Seq Idle hwrite haddr Read V1 V2 hready weim_hrdata Last Valid Data V1 Word V2 Word weim_hready BCLK (burst clock) Last ADDR CS2 Address V1 R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) Read ECB DATA V1 1/2 V1 2/2 V2 1/2 V2 2/2 Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 35. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 48 Freescale Semiconductor Specifications hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans Non seq Read V1 Seq Idle hwrite haddr Read V2 hready weim_hrdata Last Valid Data V1 Word V2 Word weim_hready BCLK (burst clock) ADDR CS2 Last Address V1 R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1) Read ECB DATA V1 1/2 V1 2/2 V2 1/2 V2 2/2 Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 36. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 49 Specifications 3.9.4 Non-TFT Panel Timing T1 VSYN T1 T2 HSYN SCLK T3 XMAX T4 T2 Ts LD[15:0] Figure 37. Non-TFT Panel Timing Table 21. Symbol T1 T2 T3 T4 Parameter HSYN to VSYN delay HSYN pulse width VSYN to SCLK SCLK to HSYN Non TFT Panel Timing Diagram Allowed Register Minimum Value 0 0 - 0 Actual Value HWAIT2+2 HWIDTH+1 0<= T3<=Ts HWAIT1+1 Unit Tpix Tpix - Tpix * * * * * * VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all these 3 signals are active high. Ts is the shift clock period. Ts = Tpix * (panel data bus width). Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1). Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register. Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong. MC9328MXS Advance Information, Rev. 0 50 Freescale Semiconductor Specifications 3.10 SPI Timing Diagrams To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI module is configured as a master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). The SPI1 Sample Period Control Register (PERIODREG1) can also be programmed to a fixed data transfer rate. When the SPI module is configured as a slave, the user can configure the SPI1 Control Register (CONTROLREG1) to match the external SPI master's timing. In this configuration, SS becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data FIFO. Figure 38 through Figure 42 show the timing relationship of the master SPI using different triggering mechanisms. 2 SS 1 SPIRDY 4 3 5 SCLK, MOSI, MISO Figure 38. Master SPI Timing Diagram Using SPI_RDY Edge Trigger SS SPIRDY SCLK, MOSI, MISO Figure 39. Master SPI Timing Diagram Using SPI_RDY Level Trigger SS (output) SCLK, MOSI, MISO Figure 40. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 41. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 51 Specifications SS (input) 6 SCLK, MOSI, MISO 7 Figure 42. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge Table 22. Timing Parameter Table for Figure 38 through Figure 42 3.0 0.3 V Ref No. 1 2 3 4 5 6 7 1. 2. 3. Parameter SPI_RDY to SS output low SS output low to first SCLK edge Last SCLK edge to SS output high SS output high to SPI_RDY low SS output pulse width SS input low to first SCLK edge SS input pulse width Minimum 2T1 3 * Tsclk2 2 * Tsclk 0 Tsclk + WAIT 3 T T Maximum - - - - - - - Unit ns ns ns ns ns ns ns T = CSPI system clock period (PERCLK2). Tsclk = Period of SCLK. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register. 3.11 LCD Controller This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the i.MX Reference Manual. LSCLK 1 LD[15:0] Figure 43. SCLK to LD Timing Diagram Table 23. LCDC SCLK Timing Parameter Table 3.0 0.3 V Ref No. 1 Parameter SCLK to LD valid Minimum - Maximum 2 Unit ns MC9328MXS Advance Information, Rev. 0 52 Freescale Semiconductor Specifications Non-display region T1 T3 Display region T4 VSYN HSYN OE LD[15:0] T2 Line Y Line 1 Line Y T5 HSYN SCLK OE LD[15:0] VSYN T6 XMAX T7 T8 (1,1) (1,2) (1,X) T9 T10 Figure 44. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table 24. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T9 Description End of OE to beginning of VSYN HSYN period VSYN pulse width End of VSYN to beginning of OE HSYN pulse width End of HSYN to beginning to T9 End of OE to beginning of HSYN SCLK to valid LD data End of HSYN idle2 to VSYN edge (for non-display region) End of HSYN idle2 to VSYN edge (for Display region) Minimum T5+T6 +T7+T9 XMAX+5 T2 2 1 1 1 -3 2 1 Corresponding Register Value (VWAIT1*T2)+T5+T6+T7+T9 XMAX+T5+T6+T7+T9+T10 VWIDTH*(T2) VWAIT2*(T2) HWIDTH+1 HWAIT2+1 HWAIT1+1 3 2 1 Unit Ts Ts Ts Ts Ts Ts Ts ns Ts Ts MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 53 Specifications Table 24. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued) Symbol T10 T10 Note: * * * * * * Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns. VSYN, HSYN and OE can be programmed as active high or active low. In Figure 44, all 3 signals are active low. The polarity of SCLK and LD[15:0] can also be programmed. SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 44, SCLK is always active. For T9 non-display region, VSYN is non-active. It is used as an reference. XMAX is defined in pixels. Description VSYN to OE active (Sharp = 0) when VWAIT2 = 0 VSYN to OE active (Sharp = 1) when VWAIT2 = 0 Minimum 1 2 Corresponding Register Value 1 2 Unit Ts Ts MC9328MXS Advance Information, Rev. 0 54 Freescale Semiconductor Specifications 3.12 Pulse-Width Modulator The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal is passed through a divider and a prescaler before being input to the counter. The output is available at the pulsewidth modulator output (PWMO) external pin. Its timing diagram is shown in Figure 45 and the parameters are listed in Table 25. 2a System Clock 1 3b 2b 3a 4a PWM Output 4b Figure 45. PWM Output Timing Diagram Table 25. PWM Output Timing Parameter Table Ref No. 1 2a 2b 3a 3b 4a 4b 1. 1.8 0.1 V Parameter Minimum System CLK frequency1 Clock high time1 Clock low time1 Clock fall time1 Clock rise time1 Output delay time1 Output setup time1 CL of PWMO = 30 pF 3.0 0.3 V Unit Minimum 0 5/10 5/10 - - 5 5 Maximum 100 - - 5/10 5/10 - - MHz ns ns ns ns ns ns Maximum 87 - - 5 6.67 - - 0 3.3 7.5 - - 5.7 5.7 MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 55 Specifications 3.13 SDRAM Controller This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic random access memory) Controller. 1 SDCLK 2 3S CS 3 3S RAS 3S 3H CAS 3S 3H WE 4S ADDR 4H COL/BA 8 DQ 3H 3H ROW/BA 5 6 Data 7 3S DQM 3H Note: CKE is high during the read/write cycle. Figure 46. SDRAM Read Cycle Timing Diagram Table 26. SDRAM Read Timing Parameter Table Ref No. 1 2 3 3S 3H 1.8 0.1 V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM setup time CS, RAS, CAS, WE, DQM hold time 2.67 6 11.4 3.42 2.28 Maximum - - - - - Minimum 4 4 10 3 2 Maximum - - - - - ns ns ns ns ns 3.0 0.3 V Unit MC9328MXS Advance Information, Rev. 0 56 Freescale Semiconductor Specifications Table 26. SDRAM Read Timing Parameter Table (Continued) Ref No. 4S 4H 5 5 5 6 7 7 7 8 1. 1.8 0.1 V Parameter Minimum Address setup time Address hold time SDRAM access time (CL = 3) SDRAM access time (CL = 2) SDRAM access time (CL = 1) Data out hold time Data out high-impedance time (CL = 3) Data out high-impedance time (CL = 2) Data out high-impedance time (CL = 1) Active to read/write command period (RC = 1) 3.42 2.28 - - - 2.85 - - - tRCD1 Maximum - - 6.84 6.84 22 - 6.84 6.84 22 - Minimum 3 2 - - - 2.5 - - - tRCD1 Maximum - - 6 6 22 - 6 6 22 - ns ns ns ns ns ns ns ns ns ns 3.0 0.3 V Unit tRCD = SDRAM clock cycle time. This settings can be found in the i.MX reference manual. MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 57 Specifications SDCLK 1 CS 3 2 RAS 6 CAS WE 4 ADDR 5 7 COL/BA 8 DQ DATA 9 / BA ROW/BA DQM Figure 47. SDRAM Write Cycle Timing Diagram Table 27. SDRAM Write Timing Parameter Table Ref No. 1 2 3 4 5 6 7 1.8 0.1 V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period1 Active to read/write command delay 2.67 6 11.4 3.42 2.28 tRP2 tRCD2 Maximum - - - - - - - Minimum 4 4 10 3 2 tRP2 tRCD2 Maximum - - - - - - - ns ns ns ns ns ns ns 3.0 0.3 V Unit MC9328MXS Advance Information, Rev. 0 58 Freescale Semiconductor Specifications Table 27. SDRAM Write Timing Parameter Table (Continued) Ref No. 8 9 1. 2. Data setup time Data hold time 1.8 0.1 V Parameter Minimum 4.0 2.28 Maximum - - Minimum 2 2 Maximum - - ns ns 3.0 0.3 V Unit Precharge cycle timing is included in the write timing diagram. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the i.MX reference manual. SDCLK 1 3 2 CS RAS 6 CAS 7 7 WE 4 ADDR BA 5 ROW/BA DQ DQM Figure 48. SDRAM Refresh Timing Diagram Table 28. SDRAM Refresh Timing Parameter Table Ref No. 1 2 1.8 0.1 V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width 2.67 6 Maximum - - Minimum 4 4 Maximum - - ns ns 3.0 0.3 V Unit MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 59 Specifications Table 28. SDRAM Refresh Timing Parameter Table (Continued) Ref No. 3 4 5 6 7 1. 1.8 0.1 V Parameter Minimum SDRAM clock cycle time Address setup time Address hold time Precharge cycle period Auto precharge command period 11.4 3.42 2.28 tRP1 tRC1 Maximum - - - - - Minimum 10 3 2 tRP1 tRC1 Maximum - - - - - ns ns ns ns ns 3.0 0.3 V Unit tRP and tRC = SDRAM clock cycle time. These settings can be found in the i.MX reference manual. SDCLK CS RAS CAS WE ADDR BA DQ DQM CKE Figure 49. SDRAM Self-Refresh Cycle Timing Diagram MC9328MXS Advance Information, Rev. 0 60 Freescale Semiconductor Specifications 3.14 USB Device Port Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and how they work from the ground up. Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer. USBD_AFE (Output) 1 USBD_ROE (Output) tPERIOD USBD_VPO (Output) 6 3 tVPO_ROE t ROE_VPO t VMO_ROE 4 USBD_VMO (Output) USBD_SUSPND (Output) USBD_RCV (Input) USBD_VP (Input) USBD_VM (Input) tROE_VMO 2 tFEOPT 5 Figure 50. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX) Table 29. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX) Ref No. 1 2 3 4 5 6 3.0 0.3 V Parameter Minimum tROE_VPO; USBD_ROE active to USBD_VPO low tROE_VMO; USBD_ROE active to USBD_VMO high tVPO_ROE; USBD_VPO high to USBD_ROE deactivated tVMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes SE0) tFEOPT; SE0 interval of EOP tPERIOD; Data transfer rate 83.14 81.55 83.54 248.90 160.00 11.97 Maximum 83.47 81.98 83.80 249.13 175.00 12.03 ns ns ns ns ns Mb/s Unit MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 61 Specifications USBD_AFE (Output) USBD_ROE (Output) USBD_VPO (Output) USBD_VMO (Output) USBD_SUSPND (Output) USBD_RCV (Input) 1 tFEOPR USBD_VP (Input) USBD_VM (Input) Figure 51. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX) Table 30. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX) 3.0 0.3 V Ref No. Parameter Minimum 1 tFEOPR; Receiver SE0 interval of EOP 82 Maximum - ns Unit MC9328MXS Advance Information, Rev. 0 62 Freescale Semiconductor Specifications 3.15 I2C Module The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. SDA 5 SCL 1 2 3 4 6 Figure 52. Definition of Bus Timing for I2C Table 31. I2C Bus Timing Parameter Table 1.8 0.1 V Ref No. Parameter Minimum 1 2 3 4 5 6 Hold time (repeated) START condition Data hold time Data setup time HIGH period of the SCL clock LOW period of the SCL clock Setup time for STOP condition 182 0 11.4 80 480 182.4 Maximum - 171 - - - - Minimum 160 0 10 120 320 160 Maximum - 150 - - - - ns ns ns ns ns ns 3.0 0.3 V Unit 3.16 Synchronous Serial Interface The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the transmitter and receiver each have their own clock and frame synchronization signals. Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions only during transmission. The internal and external clock timing diagrams are shown in Figure 54 through Figure 56 on page 65. Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices. MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 63 Specifications 1 STCK Output 2 STFS (bl) Output 4 6 STFS (wl) Output 8 12 10 STXD Output 11 31 SRXD Input 32 Note: SRXD input in synchronous mode only. Figure 53. SSI Transmitter Internal Clock Timing Diagram 1 SRCK Output 3 SRFS (bl) Output 5 7 SRFS (wl) Output 9 13 14 SRXD Input Figure 54. SSI Receiver Internal Clock Timing Diagram MC9328MXS Advance Information, Rev. 0 64 Freescale Semiconductor Specifications 15 16 STCK Input 17 18 STFS (bl) Input 20 22 STFS (wl) Input 24 26 STXD Output 27 28 33 SRXD Input Note: SRXD Input in Synchronous mode only 34 Figure 55. SSI Transmitter External Clock Timing Diagram 15 16 SRCK Input 17 19 SRFS (bl) Input 21 23 SRFS (wl) Input 25 29 SRXD Input 30 Figure 56. SSI Receiver External Clock Timing Diagram Table 32. SSI (Port C Primary Function) Timing Parameter Table 1.8 0.1 V Ref No. Parameter Minimum Maximum Minimum Maximum Internal Clock Operation1 (Port C Primary Function2) 1 2 3 STCK/SRCK clock period1 STCK high to STFS (bl) high 3 3 3.0 0.3 V Unit 95 1.5 -1.2 - 4.5 -1.7 83.3 1.3 -1.1 - 3.9 -1.5 ns ns ns SRCK high to SRFS (bl) high MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 65 Specifications Table 32. SSI (Port C Primary Function) Timing Parameter Table (Continued) 1.8 0.1 V Ref No. 4 5 6 7 8 9 10 11a 11b 12 13 14 Parameter Minimum STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 3 3.0 0.3 V Unit Minimum 2.2 0.1 1.3 -1.1 2.2 0.1 12.5 0.8 0.5 11.3 18.5 0 Maximum 3.8 -0.8 3.9 -1.5 3.8 -0.8 13.8 2.7 2.8 11.9 - - ns ns ns ns ns ns ns ns ns ns ns ns Maximum 4.3 -0.8 4.45 -1.5 4.33 -0.8 15.73 3.08 3.19 13.57 - - 2.5 0.1 1.48 -1.1 2.51 0.1 14.25 0.91 0.57 12.88 21.1 0 SRCK high to SRFS (wl) high STCK high to STFS (wl) low 3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low External Clock Operation (Port C Primary Function2) 15 16 17 18 19 20 21 22 23 24 25 26 27a 27b 28 29 30 STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high 3 3 92.8 27.1 61.1 - - - - - - - - 18.01 8.98 9.12 18.47 1.14 0 - - - 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 28.16 18.13 18.24 28.5 - - 81.4 40.7 40.7 0 0 0 0 0 0 0 0 15.8 7.0 8.0 16.2 1.0 0 - - - 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 24.7 15.9 16.0 25.0 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SRCK high to SRFS (bl) high STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low 3 3 STCK high to STFS (wl) high SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hole time after SRCK low Synchronous Internal Clock Operation (Port C Primary Function2) 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 15.4 0 - - 13.5 0 - - ns ns MC9328MXS Advance Information, Rev. 0 66 Freescale Semiconductor Specifications Table 32. SSI (Port C Primary Function) Timing Parameter Table (Continued) 1.8 0.1 V Ref No. Parameter Minimum Maximum Minimum Maximum Synchronous External Clock Operation (Port C Primary Function2) 33 34 1. SRXD setup before STCK falling SRXD hold after STCK falling 1.14 0 - - 1.0 0 - - ns ns 3.0 0.3 V Unit 2. 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. bl = bit length; wl = word length. Table 33. SSI (Port B Alternate Function) Timing Parameter Table Ref No. 1.8 0.1 V Parameter Minimum Maximum Minimum Maximum 3.0 0.3 V Unit Internal Clock Operation1 (Port B Alternate Function2) 1 2 3 4 5 6 7 8 9 10 11a 11b 12 13 14 STCK/SRCK clock period1 STCK high to STFS (bl) high 3 95 1.7 -0.1 3.08 1.25 1.71 -0.1 3.08 1.25 14.93 1.25 2.51 12.43 20 0 - 4.8 1.0 5.24 2.28 4.79 1.0 5.24 2.28 16.19 3.42 3.99 14.59 - - 83.3 1.5 -0.1 2.7 1.1 1.5 -0.1 2.7 1.1 13.1 1.1 2.2 10.9 17.5 0 - 4.2 1.0 4.6 2.0 4.2 1.0 4.6 2.0 14.2 3.0 3.5 12.8 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low 3 3 SRCK high to SRFS (bl) low STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low SRCK high to SRFS (wl) 3 low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low External Clock Operation (Port B Alternate Function2) 15 STCK/SRCK clock period1 92.8 - 81.4 - ns MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 67 Specifications Table 33. SSI (Port B Alternate Function) Timing Parameter Table (Continued) Ref No. 16 17 18 19 20 21 22 23 24 25 26 27a 27b 28 29 30 1.8 0.1 V Parameter Minimum STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high 3 3 3.0 0.3 V Unit Minimum 40.7 40.7 0 0 0 0 0 0 0 0 16.6 8.1 9.3 15.7 1.0 0 Maximum - - 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 25.5 18.2 18.7 26.1 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Maximum - - 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 29.07 20.75 21.32 29.75 - - 27.1 61.1 - - - - - - - - 18.9 9.23 10.60 17.90 1.14 0 SRCK high to SRFS (bl) high STCK high to STFS (bl) low 3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high 3 3 SRCK high to SRFS (wl) high STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low Synchronous Internal Clock Operation (Port B Alternate Function2) 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 18.81 0 - - 16.5 0 - - ns ns Synchronous External Clock Operation (Port B Alternate Function2) 33 34 1. SRXD setup before STCK falling SRXD hold after STCK falling 1.14 0 - - 1.0 0 - - ns ns 2. 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. bl = bit length; wl = word length. MC9328MXS Advance Information, Rev. 0 68 Freescale Semiconductor 4 Pin-Out and Package Information Table 34 illustrates the package pin assignments for the 225-contact PBGA package. Table 34. i.MX 225 PBGA Pin Assignments 1 A PB13 2 SSI1_ RXCLK PB12 3 SSI1_ TXCLK SSI1_ RXDAT SSI1_ RXFS PB9 4 USBD_ ROE USBD_ AFE SSI1_ TXFS SSI1_ TXDAT D29 5 USBD_ SUSPND USBD_ RCV PB10 6 USBD_VM 7 SSI0_ RXFS SSI0_ RXDAT UART2_ RXD QVDD4 8 SSI0_ TXCLK UART1_ TXD SSI0_ TXFS UART2_ TXD UART1_ RXD SSI0_ RXCLK NVSS NVSS QVDD1 9 SPI1_RDY 10 SPI1_ SCLK LSCLK 11 REV 12 PS 13 LD2 14 LD4 15 LD5 Freescale Semiconductor MC9328MXS Advance Information, Rev. 0 69 B PB11 USBD_ VMO USBD_ VPO USBD_ VP QVSS SPI1_SS SPL_ SPR VSYNC LD0 LD3 LD6 LD7 C D31 PB8 UART1_ RTS NVDD3 CONTRAST LD8 LD9 LD12 NVDD2 D A23 A24 NVDD1 SPI1_ MOSI SPI1_ MISO CLS HSYNC LD1 LD11 TOUT2 LD13 E A21 A22 D30 NVDD1 UART2_ RTS UART2_ CTS NVDD4 NVSS NVSS UART1_ CTS SSI0_ TXDAT NVSS NVSS NVSS OE_ ACD QVDD3 LD10 TIN PA4 PA3 F A20 A19 D28 D27 NVDD1 NVDD1 LD14 LD15 PA6 PA8 G H J A17 A15 A14 A18 A16 A12 D26 D23 D21 D25 D24 D20 NVDD1 D22 NVDD1 NVSS NVSS NVSS QVSS NVDD2 PA10 PWMO PA5 I2C_ CLK BOOT2 PA7 PA12 TCK PA11 PA14 TDO PA13 I2C_DATA BOOT1 PA9 TMS BOOT0 K A13 A11 CS2 D19 NVDD1 NVSS QVSS NVDD1 NVSS D1 TDI BIG_ ENDIAN QVSS QVDD2 SDCKE0 SDCKE1 CAS RESET_ OUT XTAL16M RESET_IN TRISTATE CLKO SDWE XTAL32K L M N P R A10 D16 A8 D14 A6 A9 D15 A7 A5 D11 D17 D13 D12 A4 EB1 D18 D10 EB0 A3 EB2 NVDD1 EB3 D9 A2 OE NVDD1 NVDD1 D8 A1 D7 CS5 CS4 CS3 D6 A0 D2 CS1 CS0 D5 SDCLK2 ECB BCLK1 PA17 MA10 D4 NVSS RW D0 MA11 LBA NVSS NVSS DQM2 DQM1 D3 POR BOOT3 DQM0 RAS DQM3 EXTAL32K Pin-Out and Package Information EXTAL16M TRST RESETSF2 AVDD1 1. 2. Burst Clock These signals are not used on the MC9328MXS and should be floated in an actual application. Pin-Out and Package Information 4.1 PBGA 225 Package Dimensions Figure 57 illustrates the 225 PBGA 13 mm x 13 mm package. Case Outline 1304B TOP VIEW NOTES: 2. 3. 4. 5. BOTTOM VIEW SIDE VIEW 1. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. Figure 57. i.MX Processor's 225 PBGA Mechanical Drawing MC9328MXS Advance Information, Rev. 0 70 Freescale Semiconductor NOTES MC9328MXS Advance Information, Rev. 0 Freescale Semiconductor 71 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. 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ARM and the ARM POWERED logo are the registered trademarks of ARM Limited. ARM9, ARM920T, and ARM9TDMI are the trademarks of ARM Limited. (c) Freescale Semiconductor, Inc. 2005. All rights reserved. MC9328MXS/D Rev. 0 1/2005 |
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